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ISL97635A
Electrical Specifications
All specifications below are tested at T A = -40°C to +85°C; V IN = 12V, EN = 5V, R SET = 36.6k Ω , unless
otherwise noted. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not production tested. (Continued)
PARAMETER
DESCRIPTION
CONDITION
MIN TYP MAX UNIT
t SU:DAT
t LOW
Data Setup Time
Clock Low Period
250
4.7
ns
μs
t HIGH
t F
t R
Clock High Period
Clock/Data Fall Time
Clock/Data Rise Time
4.0
50
300
1000
μs
ns
ns
GENERAL TIMING SPECIFICATIONS (Note 4)
t 1
Minimum Setup Time Between V IN Rising above
EN = 1, T A = +25°C, VDC capacitor < 10μF
80
μs
VUVLO with EN = 1 and SMBus Communications
t 2
Minimum Setup Time Between EN Going High with
V IN > VUVLO, T A = +25°C,
80
μs
V IN above VUVLO and SMBus Communications
VDC capacitor < 10μF
t 3
Minimum Time Between V IN Rising above VUVLO
EN = 1, T A = +25°C
4.5
ms
with EN = 1 to SMBus BL CTRL On
t 4
Minimum Time Between EN Going High with V IN
V IN > VUVLO, T A = +25°C
4.5
ms
above VUVLO to SMBus BL CTRL On
t 5
Minimum Time for LED Output to Respond to SMBus
V IN > VUVLO, EN = 1, T A = +25°C
5
μs
Data at any Levels
t 6
Response Time Between Backlight CTRL Off with
V IN > VUVLO, EN = 1, T A = +25°C
5
μs
Boost Not Switching to Backlight CTRL On with
Boost Switching
t 7
Response Time Between Backlight CTRL On with
V IN > VUVLO, EN = 1, T A = +25°C
5
μs
Boost Switching to Backlight CTRL Off with Boost
Not Switching
t 8
LED Channel Short Circuit Fault Detection to Status
V IN > VUVLO, EN = 1, T A = +25°C, LEDs
6
ms
Register Data Ready
Active
t 9
V OUT-GND Short Circuit Detection During Operation
V IN > VUVLO, EN = 1, T A = +25°C, Fault
5
μs
to Status Register Data Ready
FET used
t 10
Time Between VIN Rising Above VUVLO with
EN = 1, VDC capacitor < 10μF, T A = +25°C,
30
ms
EN = 1 and V OUT-GND Short being Reported in
Status Register
Fault FET used.
t 11
Time Between EN Going High with V IN Above
V IN > VUVLO, VDC capacitor < 10μF,
30
ms
VUVLO and a V OUT-GND Short being Reported in
Status Register
CURRENT SOURCES
T A = +25°C, Fault FET used.
V headroom
Dominant Channel Current Source Headroom at IIN
I LED = 20mA, T A = +25°C
100
mV
Pin
V RSET
I LEDmax
Voltage at RSET Pin
Maximum LED Current Per Channel
R SET = 36.6k Ω
R SET = 20.9k Ω
680
700
35
720
mV
mA
PWM GENERATOR (Note 4)
FPWM
DPWM
t MAX_PWM_OFF
Generated PWM Frequency
Duty Cycle of Generated PWM (DC-to-PWM)
Maximum PWMI Off-Time Before Shutdown
C FPWM = 27nF, C PWMO = 220nF
V PWMO = 0.3V CFPWM = 27nF
V PWMO = 1.1V CFPWM = 27nF
EN/PWMI toggles
200
90
10
28
Hz
%
%
ms
6
FN6564.2
December 22, 2008
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